1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2023 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function int mon_check();
`endif
module t
/* verilator public_flat_on */
#(
parameter int visibleParam1 = 0,
/* verilator public_off */
parameter int invisibleParam1 = 1,
/* verilator public_on */
parameter int visibleParam2 = 2
/* verilator public_off */
)
(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
input [7:0] a /* verilator public_flat_rw */;
output reg [7:0] x /* verilator public_flat_rw */;
/*verilator public_flat_rw_on @(posedge clk)*/
reg onebit;
reg [2:1] twoone;
reg [2:1] fourthreetwoone[4:3];
reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND;
// verilator lint_off ASCRANGE
reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk)*/;
/*verilator public_off*/
reg invisible1;
// verilator lint_on ASCRANGE
/*verilator public_flat_on*/
reg [31:0] count;
reg [31:0] half_count;
/*verilator public_off*/
/*verilator public_flat_rw_on*/
reg [31:0] delayed;
reg [31:0] delayed_mem [16];
/*verilator public_off*/
reg invisible2;
/*verilator public_flat_rw_on @(posedge clk)*/
reg [7:0] text_byte;
reg [15:0] text_half;
reg [31:0] text_word;
reg [63:0] text_long;
reg [511:0] text;
reg [2047:0] too_big;
/*verilator public_off*/
integer status;
/*verilator public_flat_rw_on*/
real real1;
string str1;
localparam int nullptr = 123;
/*verilator public_off*/
sub sub();
// Test loop
initial begin
count = 0;
delayed = 0;
onebit = 1'b0;
fourthreetwoone[3] = 0; // stop icarus optimizing away
text_byte = "B";
text_half = "Hf";
text_word = "Word";
text_long = "Long64b";
text = "Verilog Test module";
too_big = "some text";
real1 = 1.0;
str1 = "hello";
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef IVERILOG
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("%%Info: Checking results\n");
if (onebit != 1'b1) $stop;
if (quads[2] != 62'h12819213_abd31a1c) $stop;
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
if (text_byte != "A") $stop;
if (text_half != "T2") $stop;
if (text_word != "Tree") $stop;
if (text_long != "44Four44") $stop;
if (text != "lorem ipsum") $stop;
if (str1 != "something a lot longer than hello") $stop;
if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop;
end
always @(posedge clk) begin
count <= count + 2;
if (count[1])
half_count <= half_count + 2;
if (count == 1000) begin
if (delayed != 123) $stop;
if (delayed_mem[7] != 456) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
genvar i;
generate
for (i=1; i<=6; i=i+1) begin : arr
arr #(.LENGTH(i)) arr();
end
endgenerate
genvar k;
generate
for (k=1; k<=6; k=k+1) begin : subs
sub subsub();
end
endgenerate
endmodule : t
module sub;
reg subsig1 /*verilator public_flat_rw*/;
reg subsig2 /*verilator public_flat_rd*/;
`ifdef IVERILOG
// stop icarus optimizing signals away
wire redundant = subsig1 | subsig2;
`endif
endmodule : sub
module arr;
parameter LENGTH = 1;
/*verilator public_flat_rw_on*/
reg [LENGTH-1:0] sig;
reg [LENGTH-1:0] rfr;
reg check;
reg verbose;
/*verilator public_off*/
initial begin
sig = {LENGTH{1'b0}};
rfr = {LENGTH{1'b0}};
end
always @(posedge check) begin
if (verbose) $display("%m : %x %x", sig, rfr);
if (check && sig != rfr) $stop;
check <= 0;
end
endmodule : arr
|
