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<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="<built-in>" language="1800-2023"/>
<file id="b" filename="<command-line>" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,9" name="$root" submodname="$root" hier="$root"/>
</cells>
<netlist>
<module loc="d,7,8,7,9" name="$root" origName="$root" topModule="1" public="true">
<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk" clocker="true" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,15,22,15,23" name="t.q" dtype_id="1" vartype="logic" origName="q"/>
<var loc="d,13,10,13,13" name="t.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,14,16,14,17" name="t.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,17,22,17,29" name="t.between" dtype_id="1" vartype="logic" origName="between"/>
<var loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const loc="d,19,18,19,19" name="32'sh4" dtype_id="3"/>
</var>
<var loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1" vartype="logic" origName="q"/>
<var loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const loc="d,39,25,39,26" name="32'sh1" dtype_id="3"/>
</var>
<var loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2" vartype="logic" origName="clk"/>
<var loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1" vartype="logic" origName="d"/>
<var loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1" vartype="logic" origName="q"/>
<topscope loc="d,7,8,7,9">
<scope loc="d,7,8,7,9" name="TOP">
<varscope loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varscope loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varscope loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varscope loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
<varscope loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
<varscope loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
<varscope loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varscope loc="d,32,15,32,20" name="t.cell1.WIDTH" dtype_id="3"/>
<varscope loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
<varscope loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
<varscope loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
<varscope loc="d,39,15,39,22" name="t.cell1.IGNORED" dtype_id="3"/>
<varscope loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
<varscope loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
<varscope loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
<assignalias loc="d,15,22,15,23" dtype_id="1">
<varref loc="d,15,22,15,23" name="q" dtype_id="1"/>
<varref loc="d,15,22,15,23" name="t.q" dtype_id="1"/>
</assignalias>
<assignalias loc="d,13,10,13,13" dtype_id="2">
<varref loc="d,13,10,13,13" name="clk" dtype_id="2"/>
<varref loc="d,13,10,13,13" name="t.clk" dtype_id="2"/>
</assignalias>
<assignalias loc="d,14,16,14,17" dtype_id="1">
<varref loc="d,14,16,14,17" name="d" dtype_id="1"/>
<varref loc="d,14,16,14,17" name="t.d" dtype_id="1"/>
</assignalias>
<assignalias loc="d,34,24,34,27" dtype_id="2">
<varref loc="d,21,42,21,45" name="t.clk" dtype_id="2"/>
<varref loc="d,34,24,34,27" name="t.cell1.clk" dtype_id="2"/>
</assignalias>
<assignalias loc="d,35,30,35,31" dtype_id="1">
<varref loc="d,22,42,22,43" name="t.d" dtype_id="1"/>
<varref loc="d,35,30,35,31" name="t.cell1.d" dtype_id="1"/>
</assignalias>
<assignalias loc="d,36,30,36,31" dtype_id="1">
<varref loc="d,20,14,20,21" name="t.between" dtype_id="1"/>
<varref loc="d,36,30,36,31" name="t.cell1.q" dtype_id="1"/>
</assignalias>
<always loc="d,41,4,41,10">
<sentree loc="d,41,11,41,12">
<senitem loc="d,41,13,41,20" edgeType="POS">
<varref loc="d,41,21,41,24" name="clk" dtype_id="2"/>
</senitem>
</sentree>
<assigndly loc="d,42,8,42,10" dtype_id="1">
<varref loc="d,42,11,42,12" name="d" dtype_id="1"/>
<varref loc="d,42,6,42,7" name="t.between" dtype_id="1"/>
</assigndly>
</always>
<assignalias loc="d,48,10,48,13" dtype_id="2">
<varref loc="d,27,42,27,45" name="t.clk" dtype_id="2"/>
<varref loc="d,48,10,48,13" name="t.cell2.clk" dtype_id="2"/>
</assignalias>
<assignalias loc="d,49,16,49,17" dtype_id="1">
<varref loc="d,25,16,25,23" name="t.between" dtype_id="1"/>
<varref loc="d,49,16,49,17" name="t.cell2.d" dtype_id="1"/>
</assignalias>
<assignalias loc="d,50,22,50,23" dtype_id="1">
<varref loc="d,26,42,26,43" name="t.q" dtype_id="1"/>
<varref loc="d,50,22,50,23" name="t.cell2.q" dtype_id="1"/>
</assignalias>
<contassign loc="d,53,13,53,14" dtype_id="1">
<varref loc="d,17,22,17,29" name="t.between" dtype_id="1"/>
<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
</contassign>
</scope>
</topscope>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,34,24,34,27" id="2" name="logic"/>
<basicdtype loc="d,15,16,15,17" id="1" name="logic" left="3" right="0"/>
<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
</typetable>
</netlist>
</verilator_xml>
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