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%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: 'logic' 't3'
: ... note: In instance 't'
38 | test_out <= '{'0, '0};
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
: ... note: In instance 't'
38 | test_out <= '{'0, '0};
| ^~
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
%Error: Exiting due to
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