1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic[3:0] enable;
int cyc = 0;
Test test(.*);
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef FAIL1 enable[0] <= 1; `endif
enable[1] <= 1;
`ifdef FAIL2 enable[2] <= 1; `endif
enable[3] <= 1;
if (cyc != 0) begin
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test(
input clk,
input[3:0] enable
);
assert property (
@(posedge clk iff enable[0])
0
) else $stop;
assert property (
@(posedge clk iff enable[1])
1
);
cover property (
@(posedge clk iff enable[2])
1
) $stop;
cover property (
@(posedge clk iff enable[3])
0
) $stop;
endmodule
|
