1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`define signal(name, expr) wire [$bits(expr)-1:0] ``name = expr
module t (
`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py
rand_a, rand_b, srand_a, srand_b
);
`include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py
input rand_a;
input rand_b;
input srand_a;
input srand_b;
wire logic [63:0] rand_a;
wire logic [63:0] rand_b;
wire logic signed [63:0] srand_a;
wire logic signed [63:0] srand_b;
//////////////////////////////////////////////////////////////////////////
logic [2:0] simple;
always_comb begin
simple[0] = rand_a[0];
simple[1] = rand_a[1];
simple[2] = rand_a[2];
end
`signal(SIMPLE, simple);
logic [1:0] reassign;
always_comb begin
reassign[0] = rand_a[0];
reassign[0] = ~rand_a[0];
reassign[1] = rand_a[1];
reassign[1] = ~rand_a[1];
end
`signal(REASSIGN, reassign);
logic [1:0] use_intermediate_a;
logic [1:0] use_intermediate_b;
always_comb begin
use_intermediate_a[0] = rand_a[0];
use_intermediate_b[0] = ~use_intermediate_a[0];
use_intermediate_a[1] = rand_a[1];
use_intermediate_a[0] = ~rand_a[0];
use_intermediate_b[1] = ~use_intermediate_a[1];
use_intermediate_a[1] = ~rand_a[1];
end
`signal(USE_INTERMEDIATE, {use_intermediate_a, use_intermediate_b});
logic [2:0] self_circular;
always_comb begin
self_circular[0] = rand_a[0];
self_circular[1] = ~self_circular[0];
self_circular[2] = ~self_circular[1];
end
`signal(SELF_CIRCULAR, self_circular);
logic [2:0] part_circular;
always_comb begin
part_circular[0] = rand_a[0];
part_circular[1] = ~part_circular[0];
end
// part_circular[2] deliberately undriven!
`signal(PART_CIRCULAR, part_circular);
logic [3:0] split_circular;
always_comb begin
split_circular[0] = rand_a[0];
split_circular[2] = rand_a[1];
end
always_comb begin
split_circular[1] = ~split_circular[0];
split_circular[3] = ~split_circular[2];
end
`signal(SPLIT_CIRCULAR, split_circular);
logic [3:0] conditional_a;
always_comb begin
conditional_a = 4'd0;
if (rand_a[0]) begin
conditional_a = rand_b[3:0];
end else begin
conditional_a = ~rand_b[3:0];
end
end
`signal(CONDITONAL_A, conditional_a);
logic [3:0] conditional_b;
always_comb begin
conditional_b = 4'd0;
if (rand_a[0]) begin
conditional_b = rand_b[3:0];
end
end
`signal(CONDITONAL_B, conditional_b);
// verilator lint_off LATCH
logic [3:0] conditional_c;
always_comb begin // nosynth
if (rand_a[0]) begin
conditional_c = rand_b[3:0];
end
if (~rand_a[0]) begin
conditional_c = ~rand_b[3:0];
end
end
`signal(CONDITONAL_C, conditional_c);
// verilator lint_on LATCH
logic [3:0] conditional_d;
always_comb begin
if (rand_a[0]) begin
conditional_d = rand_b[3:0];
end else if (rand_a[1]) begin
conditional_d = ~rand_b[3:0];
end else begin
conditional_d = rand_b[7:4];
end
end
`signal(CONDITONAL_D, conditional_d);
logic [3:0] conditional_e;
always_comb begin
conditional_e = 4'd0;
if (rand_a[0]) begin
conditional_e = rand_b[3:0];
end else begin
if (rand_a[1]) begin
conditional_e = rand_b[3:0];
end else begin
conditional_e = rand_b[7:4];
end
conditional_e = ~conditional_e;
end
end
`signal(CONDITONAL_E, conditional_e);
logic condigional_f;
always_comb begin
if (rand_b[0]) begin
condigional_f = 1'h1;
if (rand_b[1]) begin
condigional_f = rand_a[0];
end
end else begin
condigional_f = 1'b0;
end
end
`signal(CONDITONAL_F, condigional_f);
logic [2:0] conditional_g;
always_comb begin
if (rand_a[0]) begin
if (rand_a[1]) begin
if (rand_a[2]) begin
conditional_g = 3'b111;
end else begin
conditional_g = 3'b011;
end
end else begin
if (rand_a[2]) begin
conditional_g = 3'b101;
end else begin
conditional_g = 3'b001;
end
end
end else begin
if (rand_a[1]) begin
if (rand_a[2]) begin
conditional_g = 3'b110;
end else begin
conditional_g = 3'b010;
end
end else begin
if (rand_a[2]) begin
conditional_g = 3'b100;
end else begin
conditional_g = 3'b000;
end
end
end
end
`signal(CONDITONAL_G, conditional_g);
logic [2:0] conditional_h;
always_comb begin
if (rand_a[0]) begin
if (rand_a[1]) begin
conditional_h = 3'b011;
if (rand_a[2]) begin
conditional_h = 3'b111;
end
end else begin
conditional_h = 3'b001;
if (rand_a[2]) begin
conditional_h = 3'b101;
end
end
end else begin
if (rand_a[1]) begin
conditional_h = 3'b010;
if (rand_a[2]) begin
conditional_h = 3'b110;
end
end else begin
conditional_h = 3'b000;
if (rand_a[2]) begin
conditional_h = 3'b100;
end
end
end
end
`signal(CONDITONAL_H, conditional_h);
logic [2:0] conditional_i;
always_comb begin // Dumbass trailing zeroes count
do begin
conditional_i = 3'd0;
if (rand_a[0]) break;
conditional_i = 3'd1;
if (rand_a[1]) break;
conditional_i = 3'd2;
if (rand_a[2]) break;
conditional_i = 3'd3;
if (rand_a[3]) break;
conditional_i = 3'd4;
end while (0);
end
`signal(CONDITONAL_I, conditional_i);
logic [2:0] conditional_j;
always_comb begin // Even more dumbass trailing ones count
do begin
conditional_j = 3'd0;
if (rand_a[0]) begin
conditional_j = 3'd1;
end else begin
break;
end
if (rand_a[1]) begin
conditional_j = 3'd2;
end else begin
break;
end
if (rand_a[2]) begin
conditional_j = 3'd3;
end else begin
break;
end
if (rand_a[3]) begin
conditional_j = 3'd4;
end
end while (0);
end
`signal(CONDITONAL_J, conditional_j);
logic [2:0] conditional_k;
always_comb begin
if (rand_b[0]) begin
do begin
conditional_k = 3'd0;
if (rand_a[0]) break;
conditional_k = 3'd1;
if (rand_a[1]) break;
conditional_k = 3'd2;
if (rand_a[2]) break;
conditional_k = 3'd3;
if (rand_a[3]) break;
conditional_k = 3'd4;
end while (0);
end else begin
do begin
conditional_k = 3'd0;
if (rand_a[0]) begin
conditional_k = 3'd1;
end else begin
break;
end
if (rand_a[1]) begin
conditional_k = 3'd2;
end else begin
break;
end
if (rand_a[2]) begin
conditional_k = 3'd3;
end else begin
break;
end
if (rand_a[3]) begin
conditional_k = 3'd4;
end
end while (0);
end
end
`signal(CONDITONAL_K, conditional_k);
logic [1:0] conditional_l_a;
logic [1:0] conditional_l_b;
always_comb begin
do begin
conditional_l_a = 2'd0;
if (rand_a[1:0] == 2'd0) break;
conditional_l_a = 2'd1;
if (rand_a[1:0] == 2'd1) break;
conditional_l_a = 2'd2;
if (rand_a[1:0] == 2'd2) break;
conditional_l_a = 2'd3;
end while (0);
do begin
conditional_l_b = 2'd0;
if (rand_b[1:0] == 2'd0) break;
conditional_l_b = 2'd1;
if (rand_b[1:0] == 2'd1) break;
conditional_l_b = 2'd2;
if (rand_b[1:0] == 2'd2) break;
conditional_l_b = 2'd3;
end while (0);
end
`signal(CONDITONAL_L, {conditional_l_b, conditional_l_a});
logic [7:0] partial_conditional_a;
always_comb begin
partial_conditional_a[1:0] = 2'd0;
if (rand_a[0]) begin
partial_conditional_a[0] = rand_b[0];
end else begin
partial_conditional_a[1] = rand_b[1];
end
partial_conditional_a[4:3] = rand_b[4:3];
end
`signal(PARTIAL_CONDITONAL_A, partial_conditional_a);
logic [3:0] partial_conditional_b;
always_comb begin
partial_conditional_b[1:0] = 2'd0;
if (rand_a[0]) begin
partial_conditional_b[0] = rand_b[0];
end
if (rand_a[1]) begin
partial_conditional_b[1] = rand_b[1];
end
end
`signal(PARTIAL_CONDITONAL_B, partial_conditional_b);
logic [3:0] becomes_full;
always_comb begin
becomes_full[2:0] = rand_a[2:0];
becomes_full[3] = ~rand_a[3];
if (rand_b[0]) begin
becomes_full = ~becomes_full;
end
end
`signal(BECOMES_FULL, becomes_full);
// verilator lint_off LATCH
logic [3:0] latch_a;
logic [3:0] latch_b;
always_comb begin // nosynth
if (rand_b[0]) begin
latch_a[3:1] = ~rand_a[3:1];
end
latch_b = latch_a;
end
assign latch_a[0] = rand_a[0];
`signal(LATCH, latch_b);
// verilator lint_on LATCH
// verilator lint_off MULTIDRIVEN
logic static_temporary_a;
logic static_temporary_b;
logic static_temporary_tmp;
always_comb begin // revert
static_temporary_tmp = rand_a[0];
static_temporary_a = ~static_temporary_tmp;
end
always_comb begin // revert
static_temporary_tmp = static_temporary_a;
static_temporary_b = ~static_temporary_tmp;
end
// verilator lint_on MULTIDRIVEN
`signal(STATIC_TEMPORARY, {static_temporary_tmp, static_temporary_b, static_temporary_a, rand_a[0]});
logic [2:0] partial_temporary_a;
logic [2:0] partial_temporary_tmp;
always_comb begin
partial_temporary_tmp[2] = rand_a[3];
partial_temporary_tmp[1] = rand_a[2];
partial_temporary_tmp[0] = rand_a[1];
partial_temporary_a = partial_temporary_tmp;
end
`signal(PARTIAL_TEMPORARY, partial_temporary_a);
logic circular_0_x;
logic circular_0_y;
logic circular_0_z;
always_comb begin
circular_0_x = 1'b0;
circular_0_y = 1'd0;
if (rand_b[0]) begin
circular_0_x = 1'b1;
if (circular_0_z) begin
circular_0_y = 1'd1;
end
end
end
assign circular_0_z = circular_0_x & rand_a[0];
`signal(CIRCULAR_0, {circular_0_x, circular_0_y, circular_0_z});
logic [2:0] nsp_a; // Non series-parallel CFG
always_comb begin
do begin
nsp_a = 3'd0; // BB 0 -> BB 1 / BB 2
if (rand_a[1:0] == 2'd0) begin
nsp_a = 3'd1; // BB 1 -> BB 4
end else begin
nsp_a = 3'd2; // BB 2 -> BB 3 / BB 4
if (rand_a[1:0] == 2'd1) begin
nsp_a = 3'd3; // BB3 -> BB 5
break;
end
end
nsp_a = 3'd4; // BB 4 -> BB 5
end while (0);
//nsp_a = 3'd5; // BB 5
end
`signal(NSP_A, nsp_a);
logic [2:0] nsp_b; // Non series-parallel CFG
always_comb begin
do begin
nsp_b = 3'd0;
if (rand_a[1:0] == 2'd0) begin
nsp_b = 3'd1;
end else begin
nsp_b = 3'd2;
if (rand_a[1:0] == 2'd1) begin
nsp_b = 3'd3;
break;
end else begin
nsp_b = 3'd4;
if (rand_a[1:0] == 2'd2) begin
nsp_b = 3'd5;
end else begin
nsp_b = 3'd6;
break;
end
end
end
nsp_b = 3'd7;
end while (0);
end
`signal(NSP_B, nsp_b);
logic [2:0] part_sp_a; // Contains series-parallel sub-graph CFG
always_comb begin
do begin
part_sp_a = 3'd0;
if (rand_a[0]) begin
part_sp_a = 3'd1;
if (rand_a[1]) begin
part_sp_a = 3'd2;
end
end else begin
part_sp_a = 3'd3;
if (rand_a[2]) begin
part_sp_a = 3'd4;
if (rand_a[3]) begin
part_sp_a = 3'd5;
end
break;
end
end
part_sp_a = 3'd6;
if (rand_a[4]) begin
part_sp_a = 3'd7;
end
end while (0);
end
`signal(PART_SP_A, part_sp_a);
logic [1:0] both_break;
always_comb begin
do begin
if (rand_a[0]) begin
both_break = 2'd0;
break;
end else begin
both_break = 2'd1;
break;
end
// Unreachable
if (rand_a[1]) begin
both_break = 2'd2;
end
end while(0);
end
`signal(BOTH_BREAK, both_break);
endmodule
|
