1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
// DESCRIPTION: Verilator: Test for issue #2267
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by James Pallister.
// SPDX-License-Identifier: CC0-1.0
module mod_a;
mod_inner u_inner();
mod_a_mon u_a_mon();
initial begin
bit x;
u_inner.x = 1;
u_a_mon.y = 0;
u_a_mon.accessor;
if (u_a_mon.y != 1) begin
$write("%%Error: Incorrect value placed in submodule\n");
$stop;
end
u_inner.x = 0;
u_a_mon.accessor;
if (u_a_mon.y != 0) begin
$write("%%Error: Incorrect value placed in submodule\n");
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : mod_a
module mod_inner;
logic x;
endmodule : mod_inner
module mod_a_mon;
bit y;
function automatic void accessor;
begin : accessor_block
bit read_x = mod_a.u_inner.x;
y = read_x;
end
endfunction
endmodule
|
