1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
interface inf;
int v;
int o;
modport mp (
input o
);
endinterface
module GenericModule (interface.mp a);
initial begin
#1;
if (a.v != 7) $stop;
end
endmodule
module t;
inf inf_inst();
GenericModule genericModule (inf_inst);
initial begin
inf_inst.v = 7;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
