File: t_interface_virtual_unused.v

package info (click to toggle)
verilator 5.040-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 164,628 kB
  • sloc: cpp: 145,372; python: 21,412; ansic: 10,559; yacc: 6,085; lex: 1,931; makefile: 1,264; sh: 494; perl: 282; fortran: 22
file content (20 lines) | stat: -rw-r--r-- 419 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Arkadiusz Kozdra.
// SPDX-License-Identifier: CC0-1.0

// See also t_interface_virtual.v

interface QBus();
endinterface

module t (/*AUTOARG*/);

   virtual QBus q8;

   initial begin
      $write("*-* All Finished *-*\n");
      $finish;
   end
endmodule