File: t_pgo_threads_hier_nested.vlt

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0

`verilator_config
hier_workers -module "Test" -workers 2
hier_block -module "Check"
hier_workers -module "Check" -workers 2