File: t_trace_binary.out

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$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module t $end
  $var wire 32 # sig [31:0] $end
 $upscope $end
$enddefinitions $end


#0
b00000000000000000000000000001010 #
#20
b00000000000000000000000000010100 #