1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
.. Copyright 2003-2026 by Wilson Snyder.
.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
.. _example create-binary execution:
Example Create-Binary Execution
===============================
We'll compile this SystemVerilog example into a Verilated simulation
binary. For an example that discusses the next level of detail see
:ref:`Example C++ Execution`.
.. include:: example_common_install.rst
Now, let's create an example Verilog file:
.. code-block:: bash
mkdir test_our
cd test_our
cat >our.v <<'EOF'
module our;
initial begin $display("Hello World"); $finish; end
endmodule
EOF
Now we run Verilator on our little example.
.. code-block:: bash
verilator --binary -j 0 -Wall our.v
Breaking this command down:
#. :vlopt:`--binary` telling Verilator to do everything needed to create a
simulation executable.
#. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine
has.
#. :vlopt:`-Wall` so Verilator has stronger lint warnings enabled.
#. An finally, :command:`our.v`, which is our SystemVerilog design file.
And now we run it:
.. code-block:: bash
obj_dir/Vour
And we get as output:
.. code-block:: bash
Hello World
- our.v:2: Verilog $finish
You're better off using a Makefile to run the steps for you, so when your
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
that do this, see the :file:`examples` directory in the distribution.
|
