File: autoconstant_gooch.v

package info (click to toggle)
verilog-mode 20161124.fd230e6-2
  • links: PTS, VCS
  • area: main
  • in suites: buster, stretch
  • size: 3,764 kB
  • ctags: 5,143
  • sloc: lisp: 12,430; perl: 293; makefile: 146; sh: 35; fortran: 2
file content (102 lines) | stat: -rw-r--r-- 1,671 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
module autoconstant_gooch
  (/*AUTOARG*/
   // Outputs
   out1, out2, out3,
   // Inputs
   in1, in2, in3
   );

   input	[3:0]	in1;
   input [3:0] 		in2;
   input [3:0] 		in3;
   output [3:0] 	out1;
   reg [3:0] 		out1;
   output [3:0] 	out2;
   reg [3:0] 		out2;
   output [3:0] 	out3;
   reg [3:0] 		out3;



   always @(/*AUTOSENSE*/in1 or in2 or in3)
     begin
	case (in1)
	  4'b0001 :	begin
	     out1 = in2;
	  end
	  4'b0010 :	begin
	     out1 = in2 + in3;
	  end
	  4'b0100 :	begin
	     out1 = in2 - in3;
	  end
	  4'b1000 :	begin
	     out1 = in2;
	  end
	  default	:	begin
	     out1 = {4{1'b0}};
	  end
	endcase
     end


   always @(/*AUTOSENSE*/in1 or in2 or in3)
     begin
	case (in1)
	  4'b0001 :	begin
	     out2 = in2;
	  end
	  4'b0010 :	begin
	     out2 = in2 + in3;
	  end
	  4'b0100 :	begin
	     out2 = in2 - in3;
	  end
	  4'b1000 :	begin
	     out2 = in2;
	  end
	  default	:	begin
	     out2 = {4{1'b0}};
	  end
	endcase
     end


   always @(/*AUTOSENSE*/in1 or in2 or in3)
     begin
	/* AUTO_CONSTANT( temp )*/
	/* AxxxUTO_CONSTANT temp */
	out3 = in1 + in2;
	temp2 = temp;

	// ERROR here - above constant definition is not
	// correct - no braces - and so parser keeps looking
	// for the first variable it finds between a pair of
	// braces - in this case, in2. This in2 is now a
	// "constant" and is removed from all sensitivity lists.
	// ( in2 )

	case (in1)
	  4'b0001 :	begin
	     out3 = in2;
	  end
	  4'b0010 :	begin
	     out3 = in2 + in3;
	  end
	  4'b0100 :	begin
	     out3 = in2 - in3;
	  end
	  4'b1000 :	begin
	     out3 = in2;
	  end
	  default	:	begin
	     out3 = {4{1'b0}};
	  end
	endcase
     end



endmodule