File: autoinst_belkind_concat.v

package info (click to toggle)
verilog-mode 20161124.fd230e6-2
  • links: PTS, VCS
  • area: main
  • in suites: buster, stretch
  • size: 3,764 kB
  • ctags: 5,143
  • sloc: lisp: 12,430; perl: 293; makefile: 146; sh: 35; fortran: 2
file content (24 lines) | stat: -rw-r--r-- 430 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
 
module aaa (/*AUTOARG*/);

   /*AUTOOUTPUT*/
   /*AUTOINPUT*/
   /*AUTOWIRE*/

   wire u0, u1, z0, z1;
   /*
    bbb AUTO_TEMPLATE (
            .xo0 ({(u0), y0}),
            .xo1 ({y1, (u1)}),
            .xi0 ({(z0), y2}),
            .xi1 ({y3, (z1)}),
    );
    */
   bbb bbb (/*AUTOINST*/);

endmodule // aaa

module bbb (/*AUTOARG*/);
   output [1:0] xo0, xo1;
   input [1:0]  xi0, xi1;
   /*AUTOTIEOFF*/
endmodule // bbb