File: autoreginput.v

package info (click to toggle)
verilog-mode 20161124.fd230e6-2
  • links: PTS, VCS
  • area: main
  • in suites: buster, stretch
  • size: 3,764 kB
  • ctags: 5,143
  • sloc: lisp: 12,430; perl: 293; makefile: 146; sh: 35; fortran: 2
file content (21 lines) | stat: -rw-r--r-- 571 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
module autoreginput;

   /*AUTOREGINPUT*/
   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
   reg			lower_ina;		// To inst of inst.v
   reg			lower_inb;		// To inst of inst.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire			lower_out;		// From inst of inst.v
   // End of automatics

   inst inst (/*AUTOINST*/
	      // Outputs
	      .lower_out		(lower_out),
	      // Inputs
	      .lower_inb		(lower_inb),
	      .lower_ina		(lower_ina));

endmodule