File: indent_begin_clapp.v

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verilog-mode 20161124.fd230e6-2
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// bug 825
module x;

always @*
begin
end

initial
begin
end

final
begin
end

initial forever
  begin
end

foreach(1)
begin
  end

do
 begin
 end while (i);

initial @a.b
  begin
end

always @E
  begin
 end

forever @E
 begin
  end

endmodule

// Local Variables:
// verilog-indent-begin-after-if: nil
// End: