File: indent_if.v

package info (click to toggle)
verilog-mode 20161124.fd230e6-2
  • links: PTS, VCS
  • area: main
  • in suites: buster, stretch
  • size: 3,764 kB
  • ctags: 5,143
  • sloc: lisp: 12,430; perl: 293; makefile: 146; sh: 35; fortran: 2
file content (7 lines) | stat: -rw-r--r-- 124 bytes parent folder | download
1
2
3
4
5
6
7
module foo;
   initial
     if (cond1) begin
	sig1 <= {4'h0, 4'hc};
	sig2 <= 8'hff;
     end // if (cond1)
endmodule // foo