File: inject_inst_empty_ports.v

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verilog-mode 20161124.fd230e6-2
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module inject_inst_empty_ports;
  logic [7:0] q;
  logic [7:0] d;
  logic       clk, rst_n;

  register r1 (.q(q),
               .qb(), // unconnect output
               .d(d),
               .clk(clk),
               .rst_n(rst_n)
               );
endmodule

module register (
  output logic [7:0] q, qb,
  input  logic [7:0] d,
  input  logic       clk, rst_n
  );

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) q <= '0;
    else        q <= d;

  assign qb = ~q;
endmodule