File: abc.sv

package info (click to toggle)
verilog-mode 20161124.fd230e6-2
  • links: PTS, VCS
  • area: main
  • in suites: buster, stretch
  • size: 3,764 kB
  • ctags: 5,143
  • sloc: lisp: 12,430; perl: 293; makefile: 146; sh: 35; fortran: 2
file content (20 lines) | stat: -rw-r--r-- 375 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
 

covergroup CB;
   a: coverpoint tr.a
     {
      bins a0 = {0};
      bins a1 = {1};
      option.weight=0;
   }
   b: coverpoint tr.b {
      bins b0 = {0};
      bins b1 = {1};
      option.weight=0;
   }
   ab: cross a,b {
      bins a0b0 = binsof(a.a0) && binsof(b.b0);
      bins a1b0 = binsof(a.a1) && binsof(b.b0);
      bins b0 = binsof(b.b0);
   }
endgroup // CB