File: autolisp_order_bug356.v

package info (click to toggle)
verilog-mode 20161124.fd230e6-2
  • links: PTS, VCS
  • area: main
  • in suites: buster, stretch
  • size: 3,764 kB
  • ctags: 5,143
  • sloc: lisp: 12,430; perl: 293; makefile: 146; sh: 35; fortran: 2
file content (47 lines) | stat: -rw-r--r-- 1,490 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
module autolisp_top (/*AUTOARG*/);
   
   /* autolisp_inst AUTO_TEMPLATE (
    .\(.*\)A    (\1_@"(eval tense)"_A),
    .\(.*\)B    (\1_@"(eval tense)"_B),
    );
    */
   /* AUTO_LISP(setq tense "is") */
   autolisp_inst AUTOLISP_INST_I0
     (/*AUTOINST*/
      // Outputs
      .result                           (result),
      // Inputs
      .portA                            (port_is_A),             // Templated
      .busA                             (bus_is_A),              // Templated
      .portB                            (port_is_B),             // Templated
      .busB                             (bus_is_B));             // Templated
   
   /* AUTO_LISP(setq tense "was") */
   autolisp_inst AUTOLISP_INST_I1
     (/*AUTOINST*/
      // Outputs
      .result                           (result),
      // Inputs
      .portA                            (port_was_A),            // Templated
      .busA                             (bus_was_A),             // Templated
      .portB                            (port_was_B),            // Templated
      .busB                             (bus_was_B));            // Templated
   
endmodule


module autolisp_inst (/*AUTOARG*/
                      // Outputs
                      result,
                      // Inputs
                      portA, busA, portB, busB
                      );
   
   input       portA;
   input [3:0] busA;
   input       portB;
   input [1:0] busB;
   
   output      result;
   
endmodule