File: batch_li_parent.v

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verilog-mode 20161124.fd230e6-2
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module batch_li_parent (/*AUTOARG*/
                        // Inputs
                        clk, rst
                        );
   
   input rst;
   input clk;
   
   parameter WIDTH_0  = 8;
   parameter WIDTH_1  = 16;
   
   batch_li_child
     #(.WIDTH_1 (WIDTH_0),
       .WIDTH_0 (WIDTH_1))
   child
     (/*AUTOINST*/
      // Inputs
      .rst                              (rst),
      .clk                              (clk));
   
endmodule

// Local Variables:
// verilog-auto-arg-sort: t
// End: