File: debug.v

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verilog-mode 20161124.fd230e6-2
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`include "some_macros.v"

module z();
   
   $display("%t:", $time);
   a                       = b;
   casfasdf                = d;
   g                       = r;
   fgasdfasdfasdfasfdasfd <= p;
   gh                     := h;
   gf                        <=g;
   ssdf  = 5;
   f     = zsfdsdf >= f;
   
endmodule