File: verilint_113.v

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verilog-mode 20161124.fd230e6-2
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module cdl_io (/*AUTOARG*/
               // Outputs
               topsig,
               // Inputs
               clk
               );
   
   input  clk;
   output topsig;
   
   //Verilint 113 off // WARNING: in macro RSV_CDLBASE_RDWR, Multiple drivers to a flipflop
          
   reg    topsig;
`define TOPSIG  {topsig}
   
   always @ (posedge clk) begin
      `TOPSIG <= #0 1'b1;
   end
   
   task direct_write;
      input val;
      begin
         `TOPSIG  = val;
      end
   endtask
endmodule