File: xx.v

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verilog-mode 20161124.fd230e6-2
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always
  @(w or c_int)
  begin
     if ((w == 1'b0) && ((status_register[7]) == 1'b1))
       begin
          write_protect <= `TRUE ;
       end
     if (w == 1'b1)
       begin
          write_protect <= `FALSE ;
       end
  end