File: 112_riscv_support.patch

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vtk7 7.1.1%2Bdfsg2-8
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Changes taken from https://gitlab.kitware.com/vtk/vtk/blob/master/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h

--- vtk7-7.1.1+dfsg1.orig/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h
+++ vtk7-7.1.1+dfsg1/Utilities/KWIML/vtkkwiml/include/kwiml/abi.h
@@ -467,6 +467,10 @@ suppression macro KWIML_ABI_NO_VERIFY wa
 #elif defined(__XTENSA_EL__)
 # define KWIML_ABI_ENDIAN_ID KWIML_ABI_ENDIAN_ID_LITTLE
 
+/* RISC-V */
+#elif defined(__riscv) || defined(__riscv__)
+# define KWIML_ABI_ENDIAN_ID KWIML_ABI_ENDIAN_ID_LITTLE 
+
 /* Unknown CPU */
 #elif !defined(KWIML_ABI_NO_ERROR_ENDIAN)
 # error "Byte order of target CPU unknown."