File: verilog.v

package info (click to toggle)
wxwidgets2.8 2.8.7.1-1.1%2Blenny1
  • links: PTS, VCS
  • area: main
  • in suites: lenny
  • size: 226,072 kB
  • ctags: 277,896
  • sloc: cpp: 1,769,805; xml: 396,717; python: 234,264; ansic: 126,047; makefile: 49,752; sh: 14,235; asm: 284; sql: 263; lex: 194; perl: 139; yacc: 128; pascal: 95; php: 23; haskell: 20; ruby: 20; java: 18; erlang: 17; lisp: 13; tcl: 10; csh: 9; ml: 9; ada: 5
file content (33 lines) | stat: -rw-r--r-- 439 bytes parent folder | download | duplicates (6) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
 
// Syntax Highlighting Test file for Verilog
// Some Comments about this file

module toplevel(clock,reset);
 input clock;
 input reset;

 reg flop1;
 reg flop2;

 always @ (posedge reset or posedge clock)
 if (reset)
   begin
     flop1 <= 0;
     flop2 <= 1;
   end
 else
   begin
     flop1 <= flop2;
     flop2 <= flop1;
   end
endmodule

initial
 fork
   $write("A");
   $write("B");
   begin
     #1;
     $write("C");
   end
 join