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<h1>ksrc/drivers/analogy/national_instruments/mite.h</h1><a href="mite_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
<a name="l00021"></a>00021 <span class="preprocessor">#ifndef __ANALOGY_NI_MITE_H__</span>
<a name="l00022"></a>00022 <span class="preprocessor"></span><span class="preprocessor">#define __ANALOGY_NI_MITE_H__</span>
<a name="l00023"></a>00023 <span class="preprocessor"></span>
<a name="l00024"></a>00024 <span class="preprocessor">#include <linux/pci.h></span>
<a name="l00025"></a>00025
<a name="l00026"></a>00026 <span class="preprocessor">#include <<a class="code" href="analogy__driver_8h.html" title="Analogy for Linux, driver facilities.">analogy/analogy_driver.h</a>></span>
<a name="l00027"></a>00027
<a name="l00028"></a>00028 <span class="preprocessor">#define PCI_VENDOR_ID_NATINST 0x1093</span>
<a name="l00029"></a>00029 <span class="preprocessor"></span><span class="preprocessor">#define PCI_MITE_SIZE 4096</span>
<a name="l00030"></a>00030 <span class="preprocessor"></span><span class="preprocessor">#define PCI_DAQ_SIZE 4096</span>
<a name="l00031"></a>00031 <span class="preprocessor"></span><span class="preprocessor">#define PCI_DAQ_SIZE_660X 8192</span>
<a name="l00032"></a>00032 <span class="preprocessor"></span><span class="preprocessor">#define PCIMIO_COMPAT</span>
<a name="l00033"></a>00033 <span class="preprocessor"></span><span class="preprocessor">#define MAX_MITE_DMA_CHANNELS 8</span>
<a name="l00034"></a>00034 <span class="preprocessor"></span>
<a name="l00035"></a>00035 <span class="preprocessor">#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))</span>
<a name="l00036"></a>00036 <span class="preprocessor"></span>
<a name="l00037"></a>00037 <span class="keyword">struct </span>mite_dma_descriptor {
<a name="l00038"></a>00038 u32 count;
<a name="l00039"></a>00039 u32 addr;
<a name="l00040"></a>00040 u32 next;
<a name="l00041"></a>00041 u32 dar;
<a name="l00042"></a>00042 };
<a name="l00043"></a>00043
<a name="l00044"></a>00044 <span class="keyword">struct </span>mite_dma_descriptor_ring {
<a name="l00045"></a>00045 <span class="keyword">struct </span>pci_dev *pcidev;
<a name="l00046"></a>00046 u32 n_links;
<a name="l00047"></a>00047 <span class="keyword">struct </span>mite_dma_descriptor *descriptors;
<a name="l00048"></a>00048 dma_addr_t descriptors_dma_addr;
<a name="l00049"></a>00049 };
<a name="l00050"></a>00050
<a name="l00051"></a>00051 <span class="keyword">struct </span>mite_channel {
<a name="l00052"></a>00052 <span class="keyword">struct </span>mite_struct *mite;
<a name="l00053"></a>00053 u32 channel;
<a name="l00054"></a>00054 u32 dir;
<a name="l00055"></a>00055 u32 done;
<a name="l00056"></a>00056 <span class="keyword">struct </span>mite_dma_descriptor_ring *ring;
<a name="l00057"></a>00057 };
<a name="l00058"></a>00058
<a name="l00059"></a>00059 <span class="keyword">struct </span>mite_struct {
<a name="l00060"></a>00060 <span class="keyword">struct </span>list_head list;
<a name="l00061"></a>00061 a4l_lock_t lock;
<a name="l00062"></a>00062 u32 used;
<a name="l00063"></a>00063 u32 num_channels;
<a name="l00064"></a>00064
<a name="l00065"></a>00065 <span class="keyword">struct </span>mite_channel channels[MAX_MITE_DMA_CHANNELS];
<a name="l00066"></a>00066 u32 channel_allocated[MAX_MITE_DMA_CHANNELS];
<a name="l00067"></a>00067
<a name="l00068"></a>00068 <span class="keyword">struct </span>pci_dev *pcidev;
<a name="l00069"></a>00069 resource_size_t mite_phys_addr;
<a name="l00070"></a>00070 <span class="keywordtype">void</span> *mite_io_addr;
<a name="l00071"></a>00071 resource_size_t daq_phys_addr;
<a name="l00072"></a>00072 <span class="keywordtype">void</span> *daq_io_addr;
<a name="l00073"></a>00073 };
<a name="l00074"></a>00074
<a name="l00075"></a>00075 <span class="keyword">static</span> <span class="keyword">inline</span>
<a name="l00076"></a>00076 <span class="keyword">struct </span>mite_dma_descriptor_ring *mite_alloc_ring(<span class="keyword">struct</span> mite_struct *mite)
<a name="l00077"></a>00077 {
<a name="l00078"></a>00078 <span class="keyword">struct </span>mite_dma_descriptor_ring *ring =
<a name="l00079"></a>00079 kmalloc(<span class="keyword">sizeof</span>(<span class="keyword">struct</span> mite_dma_descriptor_ring), GFP_DMA);
<a name="l00080"></a>00080
<a name="l00081"></a>00081 <span class="keywordflow">if</span> (ring == NULL)
<a name="l00082"></a>00082 <span class="keywordflow">return</span> ring;
<a name="l00083"></a>00083
<a name="l00084"></a>00084 memset(ring, 0, <span class="keyword">sizeof</span>(<span class="keyword">struct</span> mite_dma_descriptor_ring));
<a name="l00085"></a>00085
<a name="l00086"></a>00086 ring->pcidev = mite->pcidev;
<a name="l00087"></a>00087 <span class="keywordflow">if</span> (ring->pcidev == NULL) {
<a name="l00088"></a>00088 kfree(ring);
<a name="l00089"></a>00089 <span class="keywordflow">return</span> NULL;
<a name="l00090"></a>00090 }
<a name="l00091"></a>00091
<a name="l00092"></a>00092 <span class="keywordflow">return</span> ring;
<a name="l00093"></a>00093 };
<a name="l00094"></a>00094
<a name="l00095"></a>00095 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> mite_free_ring(<span class="keyword">struct</span> mite_dma_descriptor_ring *ring)
<a name="l00096"></a>00096 {
<a name="l00097"></a>00097 <span class="keywordflow">if</span> (ring) {
<a name="l00098"></a>00098 <span class="keywordflow">if</span> (ring->descriptors) {
<a name="l00099"></a>00099 pci_free_consistent(
<a name="l00100"></a>00100 ring->pcidev,
<a name="l00101"></a>00101 ring->n_links *
<a name="l00102"></a>00102 <span class="keyword">sizeof</span>(<span class="keyword">struct</span> mite_dma_descriptor),
<a name="l00103"></a>00103 ring->descriptors, ring->descriptors_dma_addr);
<a name="l00104"></a>00104 }
<a name="l00105"></a>00105 kfree(ring);
<a name="l00106"></a>00106 }
<a name="l00107"></a>00107 };
<a name="l00108"></a>00108
<a name="l00109"></a>00109 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> mite_irq(<span class="keyword">struct</span> mite_struct *mite)
<a name="l00110"></a>00110 {
<a name="l00111"></a>00111 <span class="keywordflow">return</span> mite->pcidev->irq;
<a name="l00112"></a>00112 };
<a name="l00113"></a>00113 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> mite_device_id(<span class="keyword">struct</span> mite_struct *mite)
<a name="l00114"></a>00114 {
<a name="l00115"></a>00115 <span class="keywordflow">return</span> mite->pcidev->device;
<a name="l00116"></a>00116 };
<a name="l00117"></a>00117
<a name="l00118"></a>00118 <span class="keywordtype">int</span> mite_setup(<span class="keyword">struct</span> mite_struct *mite, <span class="keywordtype">int</span> use_iodwbsr_1);
<a name="l00119"></a>00119 <span class="keywordtype">void</span> mite_unsetup(<span class="keyword">struct</span> mite_struct *mite);
<a name="l00120"></a>00120 <span class="keywordtype">void</span> mite_list_devices(<span class="keywordtype">void</span>);
<a name="l00121"></a>00121 <span class="keyword">struct </span>mite_struct * mite_find_device(<span class="keywordtype">int</span> bus,
<a name="l00122"></a>00122 <span class="keywordtype">int</span> slot, <span class="keywordtype">unsigned</span> <span class="keywordtype">short</span> device_id);
<a name="l00123"></a>00123 <span class="keyword">struct </span>mite_channel *mite_request_channel_in_range(<span class="keyword">struct</span> mite_struct *mite,
<a name="l00124"></a>00124 <span class="keyword">struct</span> mite_dma_descriptor_ring *ring, <span class="keywordtype">unsigned</span> min_channel,
<a name="l00125"></a>00125 <span class="keywordtype">unsigned</span> max_channel);
<a name="l00126"></a>00126 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keyword">struct </span>mite_channel *mite_request_channel(<span class="keyword">struct</span> mite_struct
<a name="l00127"></a>00127 *mite, <span class="keyword">struct</span> mite_dma_descriptor_ring *ring)
<a name="l00128"></a>00128 {
<a name="l00129"></a>00129 <span class="keywordflow">return</span> mite_request_channel_in_range(mite, ring, 0,
<a name="l00130"></a>00130 mite->num_channels - 1);
<a name="l00131"></a>00131 }
<a name="l00132"></a>00132 <span class="keywordtype">void</span> mite_release_channel(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00133"></a>00133
<a name="l00134"></a>00134 <span class="keywordtype">void</span> mite_dma_arm(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00135"></a>00135 <span class="keywordtype">void</span> mite_dma_disarm(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00136"></a>00136 <span class="keywordtype">int</span> mite_sync_input_dma(<span class="keyword">struct</span> mite_channel *mite_chan, <a class="code" href="structa4l__subdevice.html" title="Structure describing the subdevice.">a4l_subd_t</a> *subd);
<a name="l00137"></a>00137 <span class="keywordtype">int</span> mite_sync_output_dma(<span class="keyword">struct</span> mite_channel *mite_chan, <a class="code" href="structa4l__subdevice.html" title="Structure describing the subdevice.">a4l_subd_t</a> *subd);
<a name="l00138"></a>00138 u32 mite_bytes_written_to_memory_lb(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00139"></a>00139 u32 mite_bytes_written_to_memory_ub(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00140"></a>00140 u32 mite_bytes_read_from_memory_lb(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00141"></a>00141 u32 mite_bytes_read_from_memory_ub(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00142"></a>00142 u32 mite_bytes_in_transit(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00143"></a>00143 u32 mite_get_status(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00144"></a>00144 <span class="keywordtype">int</span> mite_done(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00145"></a>00145 <span class="keywordtype">void</span> mite_prep_dma(<span class="keyword">struct</span> mite_channel *mite_chan,
<a name="l00146"></a>00146 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> num_device_bits, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> num_memory_bits);
<a name="l00147"></a>00147 <span class="keywordtype">int</span> mite_buf_change(<span class="keyword">struct</span> mite_dma_descriptor_ring *ring, <a class="code" href="structa4l__subdevice.html" title="Structure describing the subdevice.">a4l_subd_t</a> *subd);
<a name="l00148"></a>00148
<a name="l00149"></a>00149 <span class="preprocessor">#ifdef CONFIG_DEBUG_MITE</span>
<a name="l00150"></a>00150 <span class="preprocessor"></span><span class="keywordtype">void</span> mite_print_chsr(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> chsr);
<a name="l00151"></a>00151 <span class="keywordtype">void</span> mite_dump_regs(<span class="keyword">struct</span> mite_channel *mite_chan);
<a name="l00152"></a>00152 <span class="preprocessor">#endif</span>
<a name="l00153"></a>00153 <span class="preprocessor"></span>
<a name="l00154"></a>00154 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> CHAN_OFFSET(<span class="keywordtype">int</span> channel)
<a name="l00155"></a>00155 {
<a name="l00156"></a>00156 <span class="keywordflow">return</span> 0x500 + 0x100 * channel;
<a name="l00157"></a>00157 };
<a name="l00158"></a>00158
<a name="l00159"></a>00159 <span class="keyword">enum</span> mite_registers {
<a name="l00160"></a>00160 <span class="comment">/* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be</span>
<a name="l00161"></a>00161 <span class="comment"> written and read back. The bits 0x1f always read as 1.</span>
<a name="l00162"></a>00162 <span class="comment"> The rest always read as zero. */</span>
<a name="l00163"></a>00163 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
<a name="l00164"></a>00164 MITE_IODWBSR = 0xc0, <span class="comment">//IO Device Window Base Size Register</span>
<a name="l00165"></a>00165 MITE_IODWBSR_1 = 0xc4, <span class="comment">// IO Device Window Base Size Register 1</span>
<a name="l00166"></a>00166 MITE_IODWCR_1 = 0xf4,
<a name="l00167"></a>00167 MITE_PCI_CONFIG_OFFSET = 0x300,
<a name="l00168"></a>00168 MITE_CSIGR = 0x460 <span class="comment">//chip signature</span>
<a name="l00169"></a>00169 };
<a name="l00170"></a>00170 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_CHOR(<span class="keywordtype">int</span> channel) <span class="comment">// channel operation</span>
<a name="l00171"></a>00171 {
<a name="l00172"></a>00172 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x0;
<a name="l00173"></a>00173 };
<a name="l00174"></a>00174 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_CHCR(<span class="keywordtype">int</span> channel) <span class="comment">// channel control</span>
<a name="l00175"></a>00175 {
<a name="l00176"></a>00176 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x4;
<a name="l00177"></a>00177 };
<a name="l00178"></a>00178 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_TCR(<span class="keywordtype">int</span> channel) <span class="comment">// transfer count</span>
<a name="l00179"></a>00179 {
<a name="l00180"></a>00180 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x8;
<a name="l00181"></a>00181 };
<a name="l00182"></a>00182 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_MCR(<span class="keywordtype">int</span> channel) <span class="comment">// memory configuration</span>
<a name="l00183"></a>00183 {
<a name="l00184"></a>00184 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0xc;
<a name="l00185"></a>00185 };
<a name="l00186"></a>00186 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_MAR(<span class="keywordtype">int</span> channel) <span class="comment">// memory address</span>
<a name="l00187"></a>00187 {
<a name="l00188"></a>00188 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x10;
<a name="l00189"></a>00189 };
<a name="l00190"></a>00190 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_DCR(<span class="keywordtype">int</span> channel) <span class="comment">// device configuration</span>
<a name="l00191"></a>00191 {
<a name="l00192"></a>00192 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x14;
<a name="l00193"></a>00193 };
<a name="l00194"></a>00194 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_DAR(<span class="keywordtype">int</span> channel) <span class="comment">// device address</span>
<a name="l00195"></a>00195 {
<a name="l00196"></a>00196 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x18;
<a name="l00197"></a>00197 };
<a name="l00198"></a>00198 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_LKCR(<span class="keywordtype">int</span> channel) <span class="comment">// link configuration</span>
<a name="l00199"></a>00199 {
<a name="l00200"></a>00200 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x1c;
<a name="l00201"></a>00201 };
<a name="l00202"></a>00202 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_LKAR(<span class="keywordtype">int</span> channel) <span class="comment">// link address</span>
<a name="l00203"></a>00203 {
<a name="l00204"></a>00204 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x20;
<a name="l00205"></a>00205 };
<a name="l00206"></a>00206 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_LLKAR(<span class="keywordtype">int</span> channel) <span class="comment">// see mite section of tnt5002 manual</span>
<a name="l00207"></a>00207 {
<a name="l00208"></a>00208 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x24;
<a name="l00209"></a>00209 };
<a name="l00210"></a>00210 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_BAR(<span class="keywordtype">int</span> channel) <span class="comment">// base address</span>
<a name="l00211"></a>00211 {
<a name="l00212"></a>00212 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x28;
<a name="l00213"></a>00213 };
<a name="l00214"></a>00214 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_BCR(<span class="keywordtype">int</span> channel) <span class="comment">// base count</span>
<a name="l00215"></a>00215 {
<a name="l00216"></a>00216 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x2c;
<a name="l00217"></a>00217 };
<a name="l00218"></a>00218 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_SAR(<span class="keywordtype">int</span> channel) <span class="comment">// ? address</span>
<a name="l00219"></a>00219 {
<a name="l00220"></a>00220 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x30;
<a name="l00221"></a>00221 };
<a name="l00222"></a>00222 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_WSCR(<span class="keywordtype">int</span> channel) <span class="comment">// ?</span>
<a name="l00223"></a>00223 {
<a name="l00224"></a>00224 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x34;
<a name="l00225"></a>00225 };
<a name="l00226"></a>00226 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_WSER(<span class="keywordtype">int</span> channel) <span class="comment">// ?</span>
<a name="l00227"></a>00227 {
<a name="l00228"></a>00228 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x38;
<a name="l00229"></a>00229 };
<a name="l00230"></a>00230 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_CHSR(<span class="keywordtype">int</span> channel) <span class="comment">// channel status</span>
<a name="l00231"></a>00231 {
<a name="l00232"></a>00232 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x3c;
<a name="l00233"></a>00233 };
<a name="l00234"></a>00234 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> MITE_FCR(<span class="keywordtype">int</span> channel) <span class="comment">// fifo count</span>
<a name="l00235"></a>00235 {
<a name="l00236"></a>00236 <span class="keywordflow">return</span> CHAN_OFFSET(channel) + 0x40;
<a name="l00237"></a>00237 };
<a name="l00238"></a>00238
<a name="l00239"></a>00239 <span class="keyword">enum</span> MITE_IODWBSR_bits {
<a name="l00240"></a>00240 WENAB = 0x80, <span class="comment">// window enable</span>
<a name="l00241"></a>00241 };
<a name="l00242"></a>00242
<a name="l00243"></a>00243 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">unsigned</span> MITE_IODWBSR_1_WSIZE_bits(<span class="keywordtype">unsigned</span> size)
<a name="l00244"></a>00244 {
<a name="l00245"></a>00245 <span class="keywordtype">unsigned</span> order = 0;
<a name="l00246"></a>00246 <span class="keywordflow">while</span> (size >>= 1)
<a name="l00247"></a>00247 ++order;
<a name="l00248"></a>00248 BUG_ON(order < 1);
<a name="l00249"></a>00249 <span class="keywordflow">return</span> (order - 1) & 0x1f;
<a name="l00250"></a>00250 }
<a name="l00251"></a>00251
<a name="l00252"></a>00252 <span class="keyword">enum</span> MITE_UNKNOWN_DMA_BURST_bits {
<a name="l00253"></a>00253 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
<a name="l00254"></a>00254 };
<a name="l00255"></a>00255
<a name="l00256"></a>00256 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_version(u32 csigr_bits)
<a name="l00257"></a>00257 {
<a name="l00258"></a>00258 <span class="keywordflow">return</span> csigr_bits & 0xf;
<a name="l00259"></a>00259 };
<a name="l00260"></a>00260 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_type(u32 csigr_bits)
<a name="l00261"></a>00261 { <span class="comment">// original mite = 0, minimite = 1</span>
<a name="l00262"></a>00262 <span class="keywordflow">return</span> (csigr_bits >> 4) & 0xf;
<a name="l00263"></a>00263 };
<a name="l00264"></a>00264 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_mmode(u32 csigr_bits)
<a name="l00265"></a>00265 { <span class="comment">// mite mode, minimite = 1</span>
<a name="l00266"></a>00266 <span class="keywordflow">return</span> (csigr_bits >> 8) & 0x3;
<a name="l00267"></a>00267 };
<a name="l00268"></a>00268 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_imode(u32 csigr_bits)
<a name="l00269"></a>00269 { <span class="comment">// cpu port interface mode, pci = 0x3</span>
<a name="l00270"></a>00270 <span class="keywordflow">return</span> (csigr_bits >> 12) & 0x3;
<a name="l00271"></a>00271 };
<a name="l00272"></a>00272 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_dmac(u32 csigr_bits)
<a name="l00273"></a>00273 { <span class="comment">// number of dma channels</span>
<a name="l00274"></a>00274 <span class="keywordflow">return</span> (csigr_bits >> 16) & 0xf;
<a name="l00275"></a>00275 };
<a name="l00276"></a>00276 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_wpdep(u32 csigr_bits)
<a name="l00277"></a>00277 { <span class="comment">// write post fifo depth</span>
<a name="l00278"></a>00278 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> wpdep_bits = (csigr_bits >> 20) & 0x7;
<a name="l00279"></a>00279 <span class="keywordflow">if</span> (wpdep_bits == 0)
<a name="l00280"></a>00280 <span class="keywordflow">return</span> 0;
<a name="l00281"></a>00281 <span class="keywordflow">else</span>
<a name="l00282"></a>00282 <span class="keywordflow">return</span> 1 << (wpdep_bits - 1);
<a name="l00283"></a>00283 };
<a name="l00284"></a>00284 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_wins(u32 csigr_bits)
<a name="l00285"></a>00285 {
<a name="l00286"></a>00286 <span class="keywordflow">return</span> (csigr_bits >> 24) & 0x1f;
<a name="l00287"></a>00287 };
<a name="l00288"></a>00288 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> mite_csigr_iowins(u32 csigr_bits)
<a name="l00289"></a>00289 { <span class="comment">// number of io windows</span>
<a name="l00290"></a>00290 <span class="keywordflow">return</span> (csigr_bits >> 29) & 0x7;
<a name="l00291"></a>00291 };
<a name="l00292"></a>00292
<a name="l00293"></a>00293 <span class="keyword">enum</span> MITE_MCR_bits {
<a name="l00294"></a>00294 MCRPON = 0,
<a name="l00295"></a>00295 };
<a name="l00296"></a>00296
<a name="l00297"></a>00297 <span class="keyword">enum</span> MITE_DCR_bits {
<a name="l00298"></a>00298 DCR_NORMAL = (1 << 29),
<a name="l00299"></a>00299 DCRPON = 0,
<a name="l00300"></a>00300 };
<a name="l00301"></a>00301
<a name="l00302"></a>00302 <span class="keyword">enum</span> MITE_CHOR_bits {
<a name="l00303"></a>00303 CHOR_DMARESET = (1 << 31),
<a name="l00304"></a>00304 CHOR_SET_SEND_TC = (1 << 11),
<a name="l00305"></a>00305 CHOR_CLR_SEND_TC = (1 << 10),
<a name="l00306"></a>00306 CHOR_SET_LPAUSE = (1 << 9),
<a name="l00307"></a>00307 CHOR_CLR_LPAUSE = (1 << 8),
<a name="l00308"></a>00308 CHOR_CLRDONE = (1 << 7),
<a name="l00309"></a>00309 CHOR_CLRRB = (1 << 6),
<a name="l00310"></a>00310 CHOR_CLRLC = (1 << 5),
<a name="l00311"></a>00311 CHOR_FRESET = (1 << 4),
<a name="l00312"></a>00312 CHOR_ABORT = (1 << 3), <span class="comment">/* stop without emptying fifo */</span>
<a name="l00313"></a>00313 CHOR_STOP = (1 << 2), <span class="comment">/* stop after emptying fifo */</span>
<a name="l00314"></a>00314 CHOR_CONT = (1 << 1),
<a name="l00315"></a>00315 CHOR_START = (1 << 0),
<a name="l00316"></a>00316 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
<a name="l00317"></a>00317 };
<a name="l00318"></a>00318
<a name="l00319"></a>00319 <span class="keyword">enum</span> MITE_CHCR_bits {
<a name="l00320"></a>00320 CHCR_SET_DMA_IE = (1 << 31),
<a name="l00321"></a>00321 CHCR_CLR_DMA_IE = (1 << 30),
<a name="l00322"></a>00322 CHCR_SET_LINKP_IE = (1 << 29),
<a name="l00323"></a>00323 CHCR_CLR_LINKP_IE = (1 << 28),
<a name="l00324"></a>00324 CHCR_SET_SAR_IE = (1 << 27),
<a name="l00325"></a>00325 CHCR_CLR_SAR_IE = (1 << 26),
<a name="l00326"></a>00326 CHCR_SET_DONE_IE = (1 << 25),
<a name="l00327"></a>00327 CHCR_CLR_DONE_IE = (1 << 24),
<a name="l00328"></a>00328 CHCR_SET_MRDY_IE = (1 << 23),
<a name="l00329"></a>00329 CHCR_CLR_MRDY_IE = (1 << 22),
<a name="l00330"></a>00330 CHCR_SET_DRDY_IE = (1 << 21),
<a name="l00331"></a>00331 CHCR_CLR_DRDY_IE = (1 << 20),
<a name="l00332"></a>00332 CHCR_SET_LC_IE = (1 << 19),
<a name="l00333"></a>00333 CHCR_CLR_LC_IE = (1 << 18),
<a name="l00334"></a>00334 CHCR_SET_CONT_RB_IE = (1 << 17),
<a name="l00335"></a>00335 CHCR_CLR_CONT_RB_IE = (1 << 16),
<a name="l00336"></a>00336 CHCR_FIFODIS = (1 << 15),
<a name="l00337"></a>00337 CHCR_FIFO_ON = 0,
<a name="l00338"></a>00338 CHCR_BURSTEN = (1 << 14),
<a name="l00339"></a>00339 CHCR_NO_BURSTEN = 0,
<a name="l00340"></a>00340 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
<a name="l00341"></a>00341 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
<a name="l00342"></a>00342 CHCR_DIR = (1 << 3),
<a name="l00343"></a>00343 CHCR_DEV_TO_MEM = CHCR_DIR,
<a name="l00344"></a>00344 CHCR_MEM_TO_DEV = 0,
<a name="l00345"></a>00345 CHCR_NORMAL = (0 << 0),
<a name="l00346"></a>00346 CHCR_CONTINUE = (1 << 0),
<a name="l00347"></a>00347 CHCR_RINGBUFF = (2 << 0),
<a name="l00348"></a>00348 CHCR_LINKSHORT = (4 << 0),
<a name="l00349"></a>00349 CHCR_LINKLONG = (5 << 0),
<a name="l00350"></a>00350 CHCRPON =
<a name="l00351"></a>00351 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
<a name="l00352"></a>00352 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
<a name="l00353"></a>00353 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
<a name="l00354"></a>00354 };
<a name="l00355"></a>00355
<a name="l00356"></a>00356 <span class="keyword">enum</span> ConfigRegister_bits {
<a name="l00357"></a>00357 CR_REQS_MASK = 0x7 << 16,
<a name="l00358"></a>00358 CR_ASEQDONT = 0x0 << 10,
<a name="l00359"></a>00359 CR_ASEQUP = 0x1 << 10,
<a name="l00360"></a>00360 CR_ASEQDOWN = 0x2 << 10,
<a name="l00361"></a>00361 CR_ASEQ_MASK = 0x3 << 10,
<a name="l00362"></a>00362 CR_PSIZE8 = (1 << 8),
<a name="l00363"></a>00363 CR_PSIZE16 = (2 << 8),
<a name="l00364"></a>00364 CR_PSIZE32 = (3 << 8),
<a name="l00365"></a>00365 CR_PORTCPU = (0 << 6),
<a name="l00366"></a>00366 CR_PORTIO = (1 << 6),
<a name="l00367"></a>00367 CR_PORTVXI = (2 << 6),
<a name="l00368"></a>00368 CR_PORTMXI = (3 << 6),
<a name="l00369"></a>00369 CR_AMDEVICE = (1 << 0),
<a name="l00370"></a>00370 };
<a name="l00371"></a>00371 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> CR_REQS(<span class="keywordtype">int</span> source)
<a name="l00372"></a>00372 {
<a name="l00373"></a>00373 <span class="keywordflow">return</span> (source & 0x7) << 16;
<a name="l00374"></a>00374 };
<a name="l00375"></a>00375 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> CR_REQSDRQ(<span class="keywordtype">unsigned</span> drq_line)
<a name="l00376"></a>00376 {
<a name="l00377"></a>00377 <span class="comment">/* This also works on m-series when</span>
<a name="l00378"></a>00378 <span class="comment"> using channels (drq_line) 4 or 5. */</span>
<a name="l00379"></a>00379 <span class="keywordflow">return</span> CR_REQS((drq_line & 0x3) | 0x4);
<a name="l00380"></a>00380 }
<a name="l00381"></a>00381 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">int</span> CR_RL(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> retry_limit)
<a name="l00382"></a>00382 {
<a name="l00383"></a>00383 <span class="keywordtype">int</span> value = 0;
<a name="l00384"></a>00384
<a name="l00385"></a>00385 <span class="keywordflow">while</span> (retry_limit) {
<a name="l00386"></a>00386 retry_limit >>= 1;
<a name="l00387"></a>00387 value++;
<a name="l00388"></a>00388 }
<a name="l00389"></a>00389 <span class="keywordflow">if</span> (value > 0x7)
<a name="l00390"></a>00390 __a4l_err(<span class="stringliteral">"bug! retry_limit too large\n"</span>);
<a name="l00391"></a>00391
<a name="l00392"></a>00392 <span class="keywordflow">return</span> (value & 0x7) << 21;
<a name="l00393"></a>00393 }
<a name="l00394"></a>00394
<a name="l00395"></a>00395 <span class="keyword">enum</span> CHSR_bits {
<a name="l00396"></a>00396 CHSR_INT = (1 << 31),
<a name="l00397"></a>00397 CHSR_LPAUSES = (1 << 29),
<a name="l00398"></a>00398 CHSR_SARS = (1 << 27),
<a name="l00399"></a>00399 CHSR_DONE = (1 << 25),
<a name="l00400"></a>00400 CHSR_MRDY = (1 << 23),
<a name="l00401"></a>00401 CHSR_DRDY = (1 << 21),
<a name="l00402"></a>00402 CHSR_LINKC = (1 << 19),
<a name="l00403"></a>00403 CHSR_CONTS_RB = (1 << 17),
<a name="l00404"></a>00404 CHSR_ERROR = (1 << 15),
<a name="l00405"></a>00405 CHSR_SABORT = (1 << 14),
<a name="l00406"></a>00406 CHSR_HABORT = (1 << 13),
<a name="l00407"></a>00407 CHSR_STOPS = (1 << 12),
<a name="l00408"></a>00408 CHSR_OPERR_mask = (3 << 10),
<a name="l00409"></a>00409 CHSR_OPERR_NOERROR = (0 << 10),
<a name="l00410"></a>00410 CHSR_OPERR_FIFOERROR = (1 << 10),
<a name="l00411"></a>00411 CHSR_OPERR_LINKERROR = (1 << 10), <span class="comment">/* ??? */</span>
<a name="l00412"></a>00412 CHSR_XFERR = (1 << 9),
<a name="l00413"></a>00413 CHSR_END = (1 << 8),
<a name="l00414"></a>00414 CHSR_DRQ1 = (1 << 7),
<a name="l00415"></a>00415 CHSR_DRQ0 = (1 << 6),
<a name="l00416"></a>00416 CHSR_LxERR_mask = (3 << 4),
<a name="l00417"></a>00417 CHSR_LBERR = (1 << 4),
<a name="l00418"></a>00418 CHSR_LRERR = (2 << 4),
<a name="l00419"></a>00419 CHSR_LOERR = (3 << 4),
<a name="l00420"></a>00420 CHSR_MxERR_mask = (3 << 2),
<a name="l00421"></a>00421 CHSR_MBERR = (1 << 2),
<a name="l00422"></a>00422 CHSR_MRERR = (2 << 2),
<a name="l00423"></a>00423 CHSR_MOERR = (3 << 2),
<a name="l00424"></a>00424 CHSR_DxERR_mask = (3 << 0),
<a name="l00425"></a>00425 CHSR_DBERR = (1 << 0),
<a name="l00426"></a>00426 CHSR_DRERR = (2 << 0),
<a name="l00427"></a>00427 CHSR_DOERR = (3 << 0),
<a name="l00428"></a>00428 };
<a name="l00429"></a>00429
<a name="l00430"></a>00430 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> mite_dma_reset(<span class="keyword">struct</span> mite_channel *mite_chan)
<a name="l00431"></a>00431 {
<a name="l00432"></a>00432 writel(CHOR_DMARESET | CHOR_FRESET,
<a name="l00433"></a>00433 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
<a name="l00434"></a>00434 };
<a name="l00435"></a>00435
<a name="l00436"></a>00436 <span class="preprocessor">#endif </span><span class="comment">/* !__ANALOGY_NI_MITE_H__ */</span>
</pre></div></div>
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