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#---------------------------------- Ken & Ted's Software -#
# - Default Makefile for Qt -#
#---------------------------------------------------------#
# This is a default makefile for Qt by Ken Kinder, of Ken #
# & Ted's Software. None of us really understand #
# makefiles, but I managed to put together one we can use #
# with our Qt programs. #
#---------------------------------------------------------#
#----------------------------------------/System Specific\-
INCDIR = /usr/include/qt3
CFLAGS = -O3 -fno-strength-reduce -Wall -W
LFLAGS = -lqt-mt -lX11 -lXext -L/usr/X11R6/lib
SHELL = /bin/sh
CC = g++
MOC = /usr/bin/moc
#------------------------------------------/Project Files\-
HEADERS = exec.h
SOURCES = exec.cpp
OBJECTS = exec.o
SRCMOC = moc_exec.cpp
OBJMOC = moc_exec.o
TARGET = xexec
#-----------------------------------------/Implicit Rules\-
# Ye info browser sayeth "implicit rules" are instructions
# for compile that apply to certain files, and not others.
# For example, we have two implicit rules set up, for two
# types of files -- .cpp ones and .c ones.
.SUFFIXES: .cpp .c
# /\___________________________________________
# These are the suffixes of the files which we
# are making implicit rules for.
.cpp.o:
$(CC) -c $(CFLAGS) -I$(INCDIR) -o $@ $<
# /\___________________________________________
# This is our first implicit rule. It will let
# us compile files which end in .cpp, I think.
# The $() stuff is replaced with the veriables
# we defined above.
.c.o:
$(CC) -c $(CFLAGS) -I$(INCDIR) -o $@ $<
# /\___________________________________________
# Same kind of shit here, just seemingly for
# .c files...
#--------------------------------------------/Build Rules\-
# These are like your types for actually getting
# everything compiled. Each rule will be a commandline
# option. For example, the default is all, so if you just
# run make, that's the one that will be used. But if you
# run make foolish, it'll use the foolish rule.
all: $(TARGET)
# /\___________________________________________
# Basically this idiocy is common, I dunno why.
# It redirects make all to make "target" below.
$(TARGET): $(OBJECTS) $(OBJMOC)
$(CC) $(OBJECTS) $(OBJMOC) -o $(TARGET) $(LFLAGS)
# /\___________________________________________
# Now, it's going to compile our target. The
# as arguements, we take objects, and objmoc
# and they will be replaced, in the realistic
# command line which is below, tabbed over.
# BTW, you have to have instructions for a
# rule tabbed on the next line.
#
# So $(CC) will be gcc, $(OBJECTS) I guess
# would specify the object files we're using,
# and -o means output, again, to the target
# so we have the same name (fe, hello.cpp is
# (hello binary, not a.out or elf).
# LFLAGS is another variable we defined way
# up at the top of the document.
moc: $(SRCMOC)
# /\___________________________________________
# Now, this is the rule that will run if we
# say make moc. I think somehow this has to get
# ran otherwise, but I'm not sure how.
clean:
-rm -f $(OBJECTS) $(OBJMOC) $(SRCMOC) $(TARGET)
# /\___________________________________________
# We've all typed make clean some time, haven't
# we? Well, this is what it does!
#-----------------------------------------/Compile Rules?\-
# It would seem that these rules SOMEHOW get called to
# compile or specify each file. Again, we must replace
# them with real values.
exec.o: exec.cpp \
exec.h
moc_exec.o: moc_exec.cpp \
exec.h
moc_exec.cpp: exec.h
$(MOC) exec.h -o moc_exec.cpp
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