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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML Strict//EN">
<html><head><title>
Austron 2200A/2201A GPS Receivers
</title></head><body><h3>
Austron 2200A/2201A GPS Receivers
</h3><hr>
<p><h4>Synopsis</h4>
<p>Address: 127.127.10.<var>u</var>
<br>Reference ID: GPS
<br>Driver ID: GPS-AS2201
<br>Serial Port: <code>/dev/gps<var>u</var></code>; 9600 baud, 8-bits,
no parity
<br>Features: <code>tty_clk</code>, <code>ppsclock</code> (required)
<p><h4>Description</h4>
<p>This driver supports the Austron 2200A/2201A GPS/LORAN Synchronized
Clock and Timing Receiver connected via a serial port. It supports
several special features of the clock, including the Input Buffer
Module, Output Buffer Module, IRIG-B Interface Module and LORAN Assist
Module. It requires the RS232 Serial Interface module for communication
with the driver. It requires the <code>ppsclock</code> streams module
described in the <a href="ldisc.html">Line Disciplines and Streams
Drivers</a> page. It also requires a gadget box and 1-PPS level
converter, such as described in the <a href="pps.html">Pulse-per-second
(PPS) Signal Interfacing</a> page.
<p>This receiver is capable of a comprehensive and large volume of
statistics and operational data. The specific data collection commands
and attributes are embedded in the driver source code; however, the
collection process can be enabled or disabled using the flag4 flag. If
set, collection is enabled; if not, which is the default, it is
disabled. A comprehensive suite of data reduction and summary scripts is
in the ./scripts/stats directory of the xntp3 distribution.
<p>To achieve the high accuracy this device provides, it is necessary to
use the <code>ppsclock</code> feature of the xntp3 program distribution
or, alternatively, to install the kernel modifications described in the
README.kern. The clock can be wired to provide time to a single CPU or
bussed in parallel to several CPUs, with one CPU controlling the
receiver and the others just listening. Fair accuracy can be achieved in
the single-CPU configuration without use of the 1-pps signal, but in
multiple CPU configurations accuracy is severely degraded without it.
<p><h4>Monitor Data</h4>
<p>When enabled by the <code>flag4</code> fudge flag, every received
timecode is written as-is to the <code>clockstats</code> file.
<p><h4>Fudge Factors</h4>
<dl>
<dt><code>time1 <i>time</i></code>
<dd>Specifies the time offset calibration factor, in seconds and
fraction, with default 0.0.
<p><dt><code>time2 <i>time</i></code>
<dd>Not used by this driver.
<p><dt><code>stratum <i>number</i></code>
<dd>Specifies the driver stratum, in decimal from 0 to 15, with default
0.
<p><dt><code>refid <i>string</i></code>
<dd>Specifies the driver reference identifier, an ASCII string from one
to four characters, with default <code>GPS</code>.
<p><dt><code>flag1 0 | 1</code>
<dd>Not used by this driver.
<p><dt><code>flag2 0 | 1</code>
<dd>Not used by this driver.
<p><dt><code>flag3 0 | 1</code>
<dd>Enable <code>ppsclock</code> line discipline/streams module if set.
<p><dt><code>flag4 0 | 1</code>
<dd>Enable <code>clockstats</code> recording if set.
</dl>
<p>Additional Information
<p><a href="refclock.html"> Reference Clock Drivers</a>
<hr><address>David L. Mills (mills@udel.edu)</address></body></html>
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