1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
|
Source: yosys
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Uploaders: Ruben Undheim <ruben.undheim@gmail.com>,
Sebastian Kuzminsky <seb@highlab.com>,
Daniel Gröber <dxld@darkboxed.org>
Section: electronics
Priority: optional
Build-Depends: debhelper-compat (= 13),
dh-python,
tcl-dev,
libreadline-dev,
bison,
flex,
gawk,
libffi-dev,
pkg-config,
txt2man,
iverilog (>= 10.1),
python3,
berkeley-abc (>= 1.01+20221019git70cb339+dfsg-3)
Build-Depends-Indep:
texlive-base,
texlive-plain-generic,
texlive-fonts-recommended,
texlive-fonts-extra,
texlive-latex-base,
texlive-latex-extra,
texlive-font-utils,
texlive-science,
texlive-publishers,
texlive-bibtex-extra,
lmodern,
graphviz
Rules-Requires-Root: no
Standards-Version: 4.6.1
Vcs-Browser: https://salsa.debian.org/science-team/yosys
Vcs-Git: https://salsa.debian.org/science-team/yosys.git
Homepage: https://github.com/YosysHQ/yosys
Package: yosys
Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
python3-click,
${misc:Depends},
berkeley-abc (>= 1.01+20221019git70cb339+dfsg-3),
xdot
Description: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Package: yosys-dev
Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
${misc:Depends},
tcl-dev,
libffi-dev,
libreadline-dev
Description: Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
Package: yosys-doc
Section: doc
Architecture: all
Depends: ${misc:Depends}
Multi-Arch: foreign
Suggests: yosys
Description: Documentation for Yosys
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the manual.
|
