File: design_ice.v

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module design_ice(input ck, input I1, output O1);

    reg ready = 0;
    reg value;

    always @(posedge ck) begin
        if(ready) begin
            value   <= I1;
        end
        else begin
            ready   <= 1;
        end

    end


    assign O1 = value;

endmodule