1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
ram block $__ANLOGIC_BRAM_TDP_ {
abits 13;
widths 1 2 4 9 per_port;
cost 64;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
portoption "WRITEMODE" "NORMAL" {
rdwr no_change;
}
portoption "WRITEMODE" "WRITETHROUGH" {
rdwr new;
}
portoption "WRITEMODE" "READBEFOREWRITE" {
rdwr old;
}
option "RESETMODE" "SYNC" {
rdsrst zero ungated block_wr;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
}
ram block $__ANLOGIC_BRAM_SDP_ {
abits 13;
widths 1 2 4 9 18 per_port;
byte 9;
cost 64;
init no_undef;
port sr "R" {
clock anyedge;
clken;
option "RESETMODE" "SYNC" {
rdsrst zero ungated;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
clock anyedge;
clken;
}
}
ram block $__ANLOGIC_BRAM32K_ {
abits 12;
widths 8 16 per_port;
byte 8;
cost 192;
init no_undef;
port srsw "A" "B" {
clock anyedge;
clken;
portoption "WRITEMODE" "NORMAL" {
rdwr no_change;
}
portoption "WRITEMODE" "WRITETHROUGH" {
rdwr new;
}
# no reset - it doesn't really work without the pipeline
# output registers
}
}
|
