File: inv_map.v

package info (click to toggle)
yosys 0.23-6
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 20,644 kB
  • sloc: cpp: 138,485; python: 8,605; yacc: 3,451; sh: 2,358; makefile: 1,204; lex: 696; perl: 399; ansic: 371; javascript: 323; tcl: 78; vhdl: 46
file content (4 lines) | stat: -rw-r--r-- 180 bytes parent folder | download | duplicates (2)
1
2
3
4
// Any inverters not folded into LUTs are mapped to a LUT of their own
module \$__CC_NOT (input A, output Y);
	CC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));
endmodule