File: opt_muxtree.ys

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yosys 0.52-2
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read_verilog <<EOT

module uut(
    input a, b, c, d,
    output y
);  
    assign y = a ? (a ? b : c) : d;
endmodule

EOT

copy uut after
opt_muxtree after
clean

show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut