File: example.v

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (3 lines) | stat: -rw-r--r-- 109 bytes parent folder | download | duplicates (4) 
1
2
3
 
module top (input clk, input [7:0] a, b, output reg [15:0] c);
  always @(posedge clk) c <= a * b;
endmodule