1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2023 Jannis Harder <jix@yosyshq.com> <me@jix.one>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/celltypes.h"
#include "kernel/ff.h"
#include "kernel/ffinit.h"
#include "kernel/modtools.h"
#include "kernel/sigtools.h"
#include "kernel/utils.h"
#include "kernel/yosys.h"
#include <deque>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct FutureOptions {
};
struct FutureWorker {
Module *module;
FutureOptions options;
ModWalker modwalker;
SigMap &sigmap;
FfInitVals initvals;
dict<SigBit, SigBit> future_ff_signals;
FutureWorker(Module *module, FutureOptions options) :
module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap)
{
modwalker.setup(module);
initvals.set(&modwalker.sigmap, module);
std::vector<Cell *> replaced_cells;
for (auto cell : module->selected_cells()) {
if (cell->type != ID($future_ff))
continue;
module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
replaced_cells.push_back(cell);
}
for (auto cell : replaced_cells) {
module->remove(cell);
}
}
SigSpec future_ff(SigSpec sig)
{
for (auto &bit : sig) {
bit = future_ff(bit);
}
return sig;
}
SigBit future_ff(SigBit bit)
{
if (!bit.is_wire())
return bit;
auto found = future_ff_signals.find(bit);
if (found != future_ff_signals.end())
return found->second;
auto found_driver = modwalker.signal_drivers.find(bit);
if (found_driver == modwalker.signal_drivers.end() || found_driver->second.size() < 1)
log_error("No driver for future_ff target signal %s found\n", log_signal(bit));
if (found_driver->second.size() > 1)
log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
auto driver = *found_driver->second.begin();
if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit))
log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
FfData ff(&initvals, driver.cell);
if (!ff.has_clk && !ff.has_gclk)
log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
log_id(driver.cell->type));
ff.unmap_ce_srst();
// We insert all bits into the mapping, because unmap_ce_srst might
// have removed the cell which is still present in the modwalker data.
// By inserting all bits driven by th FF we ensure that we'll never use
// that stale modwalker data again.
for (int i = 0; i < ff.width; ++i) {
future_ff_signals.emplace(ff.sig_q[i], ff.sig_d[i]);
}
return future_ff_signals.at(bit);
}
};
struct FuturePass : public Pass {
FuturePass() : Pass("future", "resolve future sampled value functions") {}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" future [options] [selection]\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
FutureOptions options;
log_header(design, "Executing FUTURE pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules()) {
FutureWorker worker(module, options);
}
}
} FuturePass;
PRIVATE_NAMESPACE_END
|
