File: pack1.v

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (11 lines) | stat: -rw-r--r-- 242 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
 
// Exact reproduction of Figure 3(a) from 10.1109/92.285741.
module top(...);
	input a,b,c,d,e,f,g,h;
	wire x = !(c|d);
	wire y = !(e&f);
	wire u = !(a&b);
	wire v = !(x|y);
	wire w = !(g&h);
	output s = !(u|v);
	output t = !(v|w);
endmodule