File: pack2.v

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (15 lines) | stat: -rw-r--r-- 401 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
 
// Exact reproduction of Figure 4(a) from 10.1109/92.285741.
module top(...);
	(* $flowmap_level=1 *) input a;
	(* $flowmap_level=1 *) input b;
	(* $flowmap_level=2 *) input c;
	(* $flowmap_level=1 *) input d;
	(* $flowmap_level=3 *) input e;
	(* $flowmap_level=1 *) input f;
	wire u = !(a&b);
	wire w = !(c|d);
	wire v = !(u|w);
	wire n0 = !(w&e);
	wire n1 = !(n0|f);
	output n2 = !(v&n1);
endmodule