File: test_arith.ys

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yosys 0.52-2
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read_verilog test_arith.v
synth_ice40
rename test gate

read_verilog test_arith.v
rename test gold

miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter

synth_ice40 -top gate

read_verilog test_arith.v
rename test gold

miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter