File: bug1758.ys

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yosys 0.52-2
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read_verilog -noopt <<EOT
module gold(input i, output o);
assign o = 1'bx | i;
endmodule
EOT
copy gold coarse
copy gold fine

cd coarse
opt_expr
select -assert-none c:*

cd fine
opt_expr
select -assert-none c:*

cd
miter -equiv -flatten -make_assert -make_outputs coarse fine miter
sat -verify -prove-asserts -show-ports miter
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter2
sat -verify -prove-asserts -show-ports -enable_undef miter2