File: bug1854.ys

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yosys 0.52-2
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read_verilog << EOT
module top(input clk, input [3:0] addr, output reg [0:0] dout);
	reg [1:0] mem[0:15];
	initial begin
		mem[0] = 2'b00;
		mem[1] = 2'b01;
		mem[2] = 2'b10;
		mem[3] = 2'b11;
	end
	always @(posedge clk)
		dout <= mem[addr];
endmodule
EOT

prep -rdff

select -assert-none t:$dff