File: bug2623.ys

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (14 lines) | stat: -rw-r--r-- 155 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
 
read_rtlil << EOT

module \top
  wire output 1 \a
  wire width 0 $dummy
  cell \abc \abc
    connect \a \a
    connect \b $dummy
  end
end

EOT

opt_clean