File: bug2765.ys

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yosys 0.52-2
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read_verilog << EOT

module top(...);

input clk;
input [3:0] wa;
input [15:0] wd;
input [3:0] ra;
output [15:0] rd;

reg [15:0] mem[0:15];

integer i;
reg x;

always @(posedge clk) begin
        for (i = 0; i < 2; i = i + 1) begin
                x = i == 1;
                if (x)
                        mem[wa] <= wd;
        end
end

assign rd = mem[ra];

endmodule

EOT

proc
opt
select -assert-count 2 t:$memwr_v2
opt_mem
select -assert-count 1 t:$memwr_v2