File: bug4413.ys

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yosys 0.52-2
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read_verilog <<EOT
module top(
	input wire shift,
	input wire [4:0] data,
	output wire out
);

	wire [1:0] shift2 = shift - 1'b1;

	assign out = data >> shift2;
endmodule

EOT

equiv_opt -assert peepopt