1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
read_verilog -specify <<EOT
module top(input a, b, output o);
assign o = a & b;
endmodule
(* blackbox *)
module bb(input a, b, output o);
assign o = a | b;
specify
(a => o) = 1;
endspecify
endmodule
(* whitebox *)
module wb(input a, b, output o);
assign o = a ^ b;
endmodule
EOT
clean
select -assert-count 1 c:*
select -assert-none t:* t:$and %d
select -assert-count 3 w:*
select -assert-count 4 *
select -assert-count 3 =c:*
select -assert-count 10 =w:*
select -assert-count 13 =*
|
