File: mem_simple_4x1_tb.v

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (29 lines) | stat: -rw-r--r-- 394 bytes parent folder | download | duplicates (5) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
 
module tb;

reg clk, rst;
wire [7:0] out;
wire [4:0] counter;

uut uut (clk, rst, out, counter);

initial begin
	#5 clk <= 0;
	repeat (100) #5 clk <= ~clk;
	#5 $finish;
end

initial begin
	rst <= 1;
	repeat (2) @(posedge clk);
	rst <= 0;
end

always @(posedge clk)
	$display("%d %d %d", rst, out, counter);

initial begin
	$dumpfile("mem_simple_4x1_tb.vcd");
	$dumpvars(0, uut);
end

endmodule