File: logic_param_simple.ys

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (9 lines) | stat: -rw-r--r-- 259 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
 
read_verilog -sv <<EOT
module test_logic_param();
parameter logic                 a = 0;
parameter logic [31:0]          e = 0;
parameter logic signed          b = 0;
parameter logic unsigned        c = 0;
parameter logic unsigned [31:0] d = 0;
endmodule
EOT