1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
read_verilog <<EOT
module top(input a, output b);
wire c;
(* submod="bar" *) sub s1(a, c);
assign b = c;
endmodule
module sub(input a, output c);
assign c = a;
endmodule
EOT
hierarchy -top top
proc
design -save gold
submod
check -assert
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog <<EOT
module top(input a, output [1:0] b);
(* submod="bar" *) sub s1(a, b[1]);
assign b[0] = 1'b0;
endmodule
module sub(input a, output c);
assign c = a;
endmodule
EOT
hierarchy -top top
proc
design -save gold
submod
check -assert top
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog <<EOT
module top(input a, output [1:0] b, c);
(* submod="bar" *) sub s1(a, b[0]);
(* submod="bar" *) sub s2(a, c[1]);
assign c = b;
endmodule
module sub(input a, output c);
assign c = a;
endmodule
EOT
hierarchy -top top
proc
design -save gold
submod
check -assert top
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -reset
read_verilog <<EOT
module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
DFF s2(.D(d), .C(c), .Q(q[0]));
DFF s3(.D(d), .C(c), .Q(q[2]));
endmodule
module DFF(input D, C, output Q);
parameter INIT = 1'b0;
endmodule
EOT
hierarchy -top top
proc
submod
dffinit -ff DFF Q INIT
check -noinit -assert
design -reset
read_verilog <<EOT
module top(input d, c, output reg [2:0] q);
(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
DFF s2(.D(d), .C(c), .Q(q[0]));
DFF s3(.D(d), .C(c), .Q(q[2]));
endmodule
EOT
hierarchy -top top
proc
submod
flatten
read_verilog <<EOT
module DFF(input D, C, output Q);
endmodule
EOT
check -assert
|
