File: always_comb_latch_2.ys

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (15 lines) | stat: -rw-r--r-- 267 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
 
read_verilog -sv <<EOF
module top;
logic x;
always_comb begin
    logic y;
    if (x)
        x = 1;
    else
        y = 1;
    x = y;
end
endmodule
EOF
logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1
proc