File: always_comb_nolatch_5.ys

package info (click to toggle)
yosys 0.52-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 69,796 kB
  • sloc: ansic: 696,955; cpp: 239,736; python: 14,617; yacc: 3,529; sh: 2,175; makefile: 1,945; lex: 697; perl: 445; javascript: 323; tcl: 162; vhdl: 115
file content (15 lines) | stat: -rw-r--r-- 227 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
 
read_verilog -sv <<EOF
module top;
logic [4:0] x;
logic z;
assign z = 1'b1;
always_comb begin : foo
    x = '0;
    if (z) begin : bar
        for (int i = 0; i < 5; i++)
            x[i] = 1'b1;
    end
end
endmodule
EOF
proc