File: bug2493.ys

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yosys 0.52-2
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logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1
read_verilog <<EOT
module top1;
    wire x;
    generate
        if (1) begin
            mod y();
            assign x = y;
        end
    endgenerate
endmodule
EOT